ASIC and FPGA Verification: A Guide to Component Modeling by Richard Munden

By Richard Munden

Richard Munden demonstrates the best way to create and use simulation types for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf electronic parts. according to the VHDL/VITAL normal, those types contain timing constraints and propagation delays which are required for exact verification of today’s electronic designs.

ASIC and FPGA Verification: A advisor to part Modeling expertly illustrates how ASICs and FPGAs might be tested within the better context of a board or a method. it's a invaluable source for any fashion designer who simulates multi-chip electronic designs.

*Provides quite a few types and a truly outlined technique for acting board-level simulation.
*Covers the main points of modeling for verification of either common sense and timing.
*First publication to gather and educate suggestions for utilizing VHDL to version "off-the-shelf" or "IP" electronic elements to be used in FPGA and board-level layout verification.

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